Sanat Agrawal

Researcher & Developer

A fourth-year undergraduate at IIT Bombay from Balangir, Odisha. I blend research and technology to build intelligent systems that solve real-world problems.

I'm driven by curiosity, problem-solving, and the challenge of creating impact through both research and code.

Sanat Agrawal

01. Where I've Worked

Research Intern @ Idiap Research Institute

October 2025 - Present | Martigny, Switzerland
  • Proposed Concatenative Neural Speech Synthesis, a novel framework integrating Festival unit selection with WavLM SSL features to bypass supervised acoustic model training.
  • Engineered a direct feature concatenation pipeline combined with kNN-Voice Conversion to enable zero-shot multi-speaker synthesis on the LibriSpeech corpus.
  • Achieved +0.81 UTMOS gain in naturalness over baseline systems by leveraging HiFi-GAN vocoding and spectral smoothing in the latent space.
  • Co-authored a research paper (equal contribution) titled "Concatenative Neural Speech Synthesis", submitted to Interspeech 2026.

Founding Engineer @ Novare Talent

July 2025 - Present
  • Architected and deployed a full-stack AI-powered talent matching platform using Next.js frontend and Python FastAPI backend with Supabase for real-time database management and authentication.
  • Built intelligent AI-driven form creation and evaluation system leveraging OpenAI and Google Gemini APIs to dynamically generate customized assessments and automatically evaluate student responses with precision scoring.
  • Implemented resume parsing and intelligent matching engine with cached text processing for rapid candidate-to-opportunity matching, helping companies find best-fit talent and students discover ideal opportunities in real-time.

AI & Systems Intern @ SalesAgent.ai

June 2025 - August 2025
  • Engineered a production-grade real-time multilingual speech-to-text pipeline integrating OpenAI Whisper and Sarvamai STT with hybrid fallback mechanisms for robust transcription across English and Indian languages.
  • Implemented language detection and dynamic agent switching using LangDetect to automatically identify caller language (Hindi, Marathi, Tamil, etc.) and route to appropriate agent configuration with context preservation.
  • Developed end-to-end voice synthesis using AI4Bharat TTS for Indian language support, enabling sales agents to respond in customer's native language with natural prosody and cultural nuance.
  • Optimized streaming audio processing with chunked buffering and background VAD (Voice Activity Detection) to reduce latency by 40% while maintaining accuracy for concurrent voice agent calls.

Research Intern @ Arizona State University

May 2024 - July 2024 | Tempe, Arizona, USA
  • Lab: Power Electronics & Control Lab (Prof. Ayan Mallik) - focusing on advanced converter optimization and AI-driven control.
  • Developed a Physics-Informed Neural Network (PINN) architecture integrating TensorFlow/Keras with differential equations to estimate parametric uncertainties (inductor saturation, parasitic resistances) in Dual Active Bridge (DAB) DC-DC converters with 92% accuracy.
  • Engineered comprehensive dataset pipeline with MATLAB simulation of physics-based models, created 10k+ training samples with systematic parameter variation, and implemented data preprocessing with scikit-learn scalers for robust neural network training.
  • Validated PINN predictions against hardware experimental data and comparative MATLAB-Simulink models, achieving superior generalization compared to purely data-driven baselines across unseen parameter regimes.
  • Designed and implemented adaptive loss-optimal control algorithm leveraging PINN-estimated parameters to dynamically adjust switching commands, achieving 67% efficiency improvement under varying load and temperature conditions.

02. Education

Indian Institute of Technology, Bombay

October 2022 - May 2027

Dual Degree (B.Tech + M.Tech) in Electrical Engineering

Specialization: Communications and Signal Processing (CSP) | Minor: Centre for Machine Intelligence and Data Science (C-MInDS)

EPFL (Swiss Federal Institute of Technology)

September 2025 - February 2026

Semester exchange student pursuing advanced coursework while conducting research in Automatic Audio Processing.

Arihant Public School, Kota

April 2020 - July 2022

Pursued my senior secondary education in Science & Maths, CBSE

Secured 96.3% in CBSE Class 12th Board Examination

Little Flower School, Balangir

April 2008 - March 2020

Pursued my primary and secondary education, ICSE

Secured 97.6% in ICSE Class 10th Board Examination

03. Technical Projects

Autonomous Racing Agent

Developed an RL agent to navigate dynamic tracks using a 13x13 sensor grid. Optimized control policies via CMA-ES over 100 generations, achieving a >80% lower crash rate compared to baseline.

  • Python
  • Reinforcement Learning
  • CMA-ES

Cough-Based Disease Detection

Engineered a dual-input neural architecture (BiLSTM + CNN) achieving 96.33% accuracy in Tuberculosis detection from audio signals. Utilized SMOTE for handling imbalanced datasets.

  • Deep Learning
  • BiLSTM
  • Audio Processing

Real-time Posture Monitoring

Built a computer vision system using Mediapipe delivering <0.1s latency. Includes a Bicep Curl and Pushup detector with >90% accuracy using joint-angle analysis.

  • OpenCV
  • Mediapipe
  • Python

Dropbox AI Chat for Research Papers

AI-powered research paper analysis tool using RAG (Retrieval-Augmented Generation) for real-time data extraction. Enables researchers to quickly summarize lengthy papers and extract critical findings from unstructured documents in Dropbox/OneDrive with precision and efficiency.

  • LLMs
  • RAG
  • OpenAI API
  • Streamlit
  • Dropbox API

Smart Walker for Clinical Rehabilitation

Designed an intelligent walker equipped with load sensors and ArUco marker-based foot detection to guide patients through rehabilitation. Provides real-time haptic & visual feedback for correct weight distribution and foot placement, reducing injury risk and accelerating recovery.

  • Raspberry Pi
  • Computer Vision
  • Load Sensors
  • Hardware Design

16-bit RISC Processor

Designed a multicycle RISC processor with a 6-stage pipeline. Integrated data forwarding for hazard mitigation and implemented on FPGA.

  • Verilog
  • Computer Architecture
  • FPGA

04. Let's Connect

Get In Touch

I'm always excited to collaborate on interesting projects and discussing ideas, or just have a meaningful conversation. Whether you're exploring a research opportunity, have a creative project in mind, or simply want to chat about the intersection of engineering and innovation.
My inbox is always open and I usually respond within 24 hours.

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